This invention relates generally to semiconductor packaging. More specifically, the invention relates to the design and manufacturing process of a semiconductor package incorporating of more than one integrated circuit chip.
A semiconductor package generally connects an integrated circuit chip to the external circuitry on a printed circuit board. To use the functionality of multiple integrated circuit chips, multiple semiconductor packages are typically used to connect these chips to the printed circuit board. With integrated circuit devices increasing in speed in complexity, the bottleneck limiting high performance is often not the chips themselves, but the electrical pathways between integrated circuits. One particularly glaring example of this bottleneck exists between high performance graphics chips and the high capacity memory chips the graphics chips require. ASIC graphic chips are sometimes placed alongside packaged memory chips, but the electrical pathways limit the speed at which the graphic chips can access the memory components. Furthermore, placing memory chips alongside a graphics chip is often not space efficient, and does little to maximize circuit density. Quad flat pack (QFP) packages often used for memory chips and flip chip packages are currently manufactured separately.
One solution to this problem is to use embedded memory on the logic chip. Embedded memory allows designers to drastically increase internal bandwidth and access speeds, reduce total pin count, and improve space efficiency. However, the cost of embedded memory is still far higher than that of discrete memory chips. Embedded memory also requires a tradeoff between chip area used for storage versus chip area used for logic. Many of the advantages of embedded memory are offset by the higher costs of embedded memory technology, especially for systems where chip area is not a critical issue.
Another solution currently used is the adjacent placement of logic and memory chips in a single package. Two separate chips, often a logic chip and a memory chip, are packaged in a single multiple chip package. These multiple chip modules often comprise two wire bond chips located adjacent to one another in a single layer of a single package. The memory chip in this instance has a shorter trace to the logic chip than it would if it was packaged separately, but the trace length is still significant. Furthermore, the footprint of the chip package still covers an area much larger than that of a logic chip with embedded memory.
More recently, multi-chip packaging methods have been proposed that provided for a plurality of chips deployed in more than one layer of a package. Examples include a stack of chips connected on edges by metal lines/connectors, and a stack of chips wire-bonded, flip chip bonded and/or otherwise bonded to one another and to the package substrate. The footprint of a multi-chip package is reduced in this vertical orientation approach, but complex chip to chip interconnection techniques, such as for the stacked chip edge connection designs, may be required. Also, existing techniques may require two or more methods, such as flip chip, wire bonding, and/or tape-automated bonding, for example, for connecting chips to each other and to the package substrate. Further, existing techniques may require more vertical space, or a larger package height, to accommodate multiple IC chips and wire-bond loops.
Portable electronic products such as portable cell-phones and cameras, and smart cards require ultra-thin IC packaging technologies and are yet demanding semiconductor technologies of greater complexity.
Consequently, what is needed is an improved multi-chip package technology that will increase package density, improve performance, including increasing access speeds between chips by significantly reducing trace lengths, while not substantially increasing package height or the complexity of packaging techniques.
To achieve the foregoing, the present invention provides a vertically integrated (xe2x80x9cchip-over-chipxe2x80x9d) semiconductor package and packaging method. The invention provides higher packaging density and performance, including increased functionality, decreased signal propagation delays, improved circuit switching speed, lower thermal resistance and higher thermal dissipation measurements, relative to previous package designs. According to the invention, a semiconductor package may be composed of a flip chip (or chips) overlying one or more other flip chips, all electrically bonded to flip chip bond pads on a cavity-less semiconductor substrate. The upper and lower flips chips may be assembled in a variety of different configurations and may be thermally or electrically connected to each other. In a preferred embodiment, the flip chips, particularly the lower flip chip(s), are thinned so that the overall package height is within conventional ranges for traditional single chip packages. Packages in accordance with the invention have increased access speeds between chips and reduced total chip package footprint.
In one aspect, the invention provides a semiconductor package. The package includes a packaging substrate having a cavity-less surface and a plurality of flip chip bonding pads on the surface. The package also includes one or more lower flip chip devices, each having a top surface and a bottom surface. The one or more lower flip chip devices is electrically connected to the substrate via solder bump connectors between the bottom surface and a first potion of the flip chip bonding pads. The package additionally includes one or more upper flip chip devices overlying at least a portion of the one or more lower flip chip devices. The one or more upper flip chip devices is connected to the substrate via solder bump connectors between a substrate-facing surface and a second portion of the flip chip bonding pads.
In another aspect, the invention provides a semiconductor packaging method. The method involves electrically connecting one or more lower flip chip devices to a first portion of flip chip bonding pads on a cavity-less semiconductor substrate surface, and electrically connecting one or more upper flip chip devices overlying at least a portion of the one or more lower flip chip devices to a second portion of flip chip bonding pads on the semiconductor substrate.
These and other features and advantages of the present invention are described below with reference to the drawings.